正交幅度调制解调器的FPGA设计与仿真

摘要

Quadrature amplitude modulation(QAM) is efficient in power and bandwidth, so it has been used widely in the field of channel modulation. The common approach to implement carrier signal of QAM is based on a look-up table, which requires a huge volume of ROM to achieve high resolution. This paper proposes a CORDIC algorithm-based pipelined architecture for implementation of QAM on FPGA, which can save considerable hardware resources and improve the speed performance. According to advantages of DSP Builder, the system is designed by utilizing VHDL and Simulink module. The correctness and feasibility of this design is verified by simulation result.%正交幅度调制技术(QAM)是一种功率和带宽相对高效的信道调制技术,因此在信道调制技术中得到了广泛的应用.它的载波信号的FPGA实现一般采用查找表的方法,为了达到高精度要求,需要耗费大量的ROM资源.提出了一种基于流水线CORDIC算法的实现方案,可有效地节省FPGA的硬件资源,提高运算速度,并根据DSP开发工具DSP Builder的优点,采用VHDL文本与Simulink模型图相结合的方法进行了设计.仿真结果验证了设计的正确性及可行性.