基于 FPGA 的通用位同步器设计

摘要

A universal bit synchronizer based on the Gardner algorithm is designed in this paper. The improved Gardner algorithm structure is adopted in the synchronizer to meet the requirements of the universal demodulator based on the software radio,which means that the bit synchronization could be achieved when the rate of baseband signals is changed in a wide range. In this paper,the principle of the traditional Gardner algorithm is introduced. The improved design and FPGA⁃based implementation methods are given. In particular,the interpolation filter coefficients can be computed in real time by Farrow structure,and GA⁃TED algorithm which is independent of the carrier phase error was used in timing error detection,while parameters of the loop filter and internal controller can be set up by the external controller. At last,the simulation and test results show that the method is correct.%　　设计了一种基于 FPGA 的通用位同步器。该同步器采用改进后的 Gardner 算法结构，其中，内插滤波器采用系数实时计算的 Farrow 结构，定时误差检测采用独立于载波相位偏差的 GA⁃TED 算法，内部控制器和环路滤波器的参数可由外部控制器设置，因而可以适应较宽速率范围内的基带码元。阐述传统 Gardner 算法的原理，给出改进后的设计和 FPGA 实现方法，最后对结果进行仿真和分析，证明该方法的正确性。