基于USB 3.0接口的高速数据传输系统设计

摘要

Since the current memory test system has the prominent problems of low data transmission speed and frequent fault occurrence,a high⁃speed data transmission system based on USB 3.0 interface was designed. The FPGA is taken as the main control chip of the design. The modes of negative delay and Ping⁃Pong cache are adopted to cache the data transformed through A/D into the DDR2 SDRAM with high speed. The general programming interface GPIF II and manual DMA channel were designed to realize the high⁃speed data transmission based on USB 3.0 synchronous slave FIFO mode. The system analysis, test and experimental results show that the system has realized the high⁃speed and reliable data transmission,and can effectively solve the high⁃speed data transmission problem occurring after large⁃capacity data acquisition.%针对目前存储测试系统中存有的数据传输慢，经常出现错误的显著问题，设计基于USB 3.0接口的高速数据传输系统。该设计以FPGA作为主控芯片，采用负延迟与乒乓缓存的方式将A/D转换的数据高速缓存到DDR2 SDRAM中。设计了GPIF Ⅱ通用可编程接口和手动 DMA 通道，实现了USB 3.0同步从FIFO模式的高速数据传输。系统分析测试和实验结果表明，该系统实现了数据的高速可靠传输，能有效解决大容量数据采集后的数据高速传输问题。