用于APFC的低功耗MOSFET驱动电路没计

摘要

设计了一款用于驱动有源功率因数校正外部功率MOSFET的驱动电路.该电路包括电平移位和图腾柱输出级两个部分.电平移位采用电流镜结构,通过控制偏置电流降低电路功耗.图腾柱输出级通过加入死区时间降低功耗,并将高压P管的栅电压箝位在6V和11V之间,不仅能够降低功耗,也节省了版图面积.基于0.4μm BCD工艺,采用HSPICE仿真结果表明,在VDD为14V,开关频率为75 kHz时,整体电路的功耗约为7.34mW,并节约了15%的版图面积.%A drive circuit for driving an external power MOSFET is designed for active power factor correction (APFC), which consists of a level-shift circuit and a single totem-pole output stage. The level-shift circuit adopts the current mirror structure so that it can reduce the power dissipation by adjusting the bias current. The dead time in the single totem-pole output stage can also decrease the power dissipation. Clamping the control signal VGs for the high voltage PMOS between 6 V and 11 V not only makes low consumption but also saves the layout area. Based on the 0. 4 μm BCD process, simulation results show that the better circuit power is 7. 34 mW and that the layout area can be saved by 15％ when VDD is 14 V and switch frequency is 75 kHz.