Globally asynchronous locally synchronous (GALS) combined with frequency scaling has become a popular and effective technique in chip power reduction. However, frequency switching penalty and crossing-domain communication may be harmful to the performance of design. This paper introduces a counter-based frequency scaling method, in which the new clock edges are generated according to the results of the counter. Based on this method a globally ratiochronous locally synchronous (GRLS) scheme is proposed. GRLS is targeting at communication between two clock domains whose frequencies are ratio-related. By use of the relationship on frequency and phase, synchronous mechanisms are employed to maintain the correctness and robustness of the scheme. GRLS achieves a zero-latency crossing-domain communication. Frequency switching can be finished in a cycle and the power and area penalties can be neglected. Experimental results of a memory system built with GRLS demonstrated its efficiency, and GRLS has been successfully applied in a commercial SoC.%全局异步局部同步(GALS)与频率调整相结合能够有效地降低动态功耗.针对频率切换以及跨时钟域传输开销会损害芯片性能的问题,提出一种基于计数器的分频方法.该方法根据计数结果生成分频后的时钟沿,并在此基础上建立了一个全局比例同步局部同步(GRLS)的通信机制.GRIS利用2个时钟的频率及相位关系实现了零延迟的跨时钟域传输,并引进同步电路分析方法来保证其正确性和健壮性；GRIS不会对原有的时钟设计做任何改变,频率切换可以在一个周期内完成,且面积功耗开销可以忽略不计.最后通过基于GRLS建立的存储系统证明了该机制的高效性.目前GRLS已经成功地应用于一款商业SoC.
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