基于HMC830的低相噪低杂散频率源的设计

摘要

To deal with the problem that phase noise worsens the SNR of sampling data and spurious degrades the sensitivity of thereceiver, a method of low phase noise and low spurious is presented. The method designs with the help of HMC830 integrated with VCO from Hittite. Several low noise regulators are used as the power supply, and reference frequency source is OCXO from Pascall. Loop filter is passive and four-order designed under the Hittite PLL Design software.Additionally, C8051F30OMCU is used to do register operation in the PLL chip. Experimental results show that in integer mode when the PD frequency is 100 MHz and output frequency is 1.8 GHz,the phase noise is -112.2 dBc/Hz@1 kHz and the spurious suppression ratio is -75.6 dBc.%针对频率源的相噪会恶化采样数据的信噪比，杂散会降低接收机灵敏度，提出了一种低相噪低杂散的设计方法。该方法利用Hittite公司的新推出的集成VCO的锁相环芯片HMC830进行设计．供电部分采用多个低噪声稳压芯片，参考频率源为Pascall公司的OCXO晶振，环路滤波器为无源四阶，使用Hittite PLL Design软件进行设计，另外采用C8051F300单片机对锁相环芯片进行寄存器操作。实验结果显示：鉴相频率为100MHz，输出频率为1．8GHz时，整数分频模式下,相位噪声为-112．2dBc/Hz@1kHz，杂散抑制度为-75．6dBc。