一种基于降压DC-DC转换器的高性能误差放大器设计

摘要

Combined with the working principle of Buck DC-DC converter, a high performance error-amplifier circuit, which met the system requirements, was presented. The input stage of the proposed error amplifier used bias current cancellation structure to reduce the impact on the reference voltage. By inducing positive feedback structure and negative feedback resistor, performance of the circuit were improved remarkably. The error-amplifier was designed and implemented by CSMC 0.5μm BCD process. The simulation results show that thetransconductance is 1.5 mS, the input common-mode voltage can begin from zero, the common mode rejection ratio is 106 dB, input offset voltage is 208.3μV, the power consumption is 100μW, which proves a good performance of the amplifier.%基于降压型DC-DC转换器的工作原理，从系统需要出发，提出一种高性能的误差放大器。该误差放大器的输入级采用偏置电流消除结构，避免其输入对基准电压产生影响；核心电路采用对称性的差分运放结构，引入正反馈结构和负反馈电阻以提高其性能，电路结构采用CSMC 0.5μm BCD工艺。仿真结果表明该误差放大器跨导为1.5 mS，共模下限可以从0开始，共模抑制比为106 dB，失调电压为208.3μV，功耗约为100μW，验证了该放大器的良好性能。