A detailed analysis is made on the TF/MC DS-CDMA system architecture and synchronization issues. According to TF/MC DS-CDMA with OFDM structure, an algorithm using the maximum likelihood is proposed to complete the system frame synchronization. It is noticed that TF/MC DS-CDMA can accommodate more users and data, and the maximum likelihood algorithm cost much hardware resource for enormous computation, so two RAM cache and move sum module with mobile windows accumulation and CP adjustable length is proposed to reduce the cost of system hardware resources and improve the synchronization module speed. The result of the timing simulation of synchronization module which is made in Quartus II 7.2 tool platform expressed that module circuit can detect the frame alignment of each frame accurately, and the precision is guaranteed at lower level of hardware cost. The design demands are achieved.%对TF/MC DS-CDMA(time-frequency-domain spread Multicarrier DS-CDMA)系统结构和同步问题进行了详细的分析,根据TF/MC DS-CDMA具有OFDM结构的特点,提出了利用最大似然算法完成整个系统的帧同步,针对最大似然算法运算量和硬件开销大以及TF/MC DS-CDMA可容纳用户及数据量多的特点,在FPGA实现中提出了利用双RAM缓存数据并且在移动求和模块中采用移动窗累加、CP长度可调等措施,一定程度上减少了系统的硬件资源开销,提高了同步模块的运行速度.在QuartusⅡ7.2工具平台上对同步模块电路进行了时序仿真,仿真结果表明,模块电路可以准确地检测到每帧数据的帧同步点,在减少硬件资源开销的同时能够保证整个同步模块的精度,满足预期要求.
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