多码率串并Viterbi译码器优化设计

摘要

In order to reduce the hardware complexity, the structural characteristics of the Viterbi decoder were studied.The branch measure unit was optimized by analyzing the characteristics of convolutional codes.Result show that the calculated branch metric value reduces from 16 to 4.The parameters of trace back unit can be configured by the backtracking algorithm with high flexibility and speed.Besides, the multi-rate punctured convolutional codes of CCSDS are acomplished by the same hardware architecture.60％ of the resources are saved compared with the normal serial-parallel structure with the same decoding speed.The throughput is as 8 times as the normal serial-parallel structure with the same hardware resources.%为了降低Viterbi译码器的硬件复杂度,对其结构特点进行了研究.通过分析卷积码的特点,对支路度量单元进行了优化,使每次所计算的支路度量值从16个减少到4个.使用灵活快速的回溯算法实现了回溯参数可配置;用同一个硬件结构实现了对CCSDS标准中的多码率删余卷积码的译码.优化结构与传统串并结构相比,译码速度相同,硬件资源可节省60%;与传统串行结构相比,硬件资源基本相同,译码速度达到了串行结构的8倍.