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基于折叠重排的低功耗BIST技术研究

     

摘要

In order to reduce test power, this paper presented a new low-power test vector generated programe,which was used LFSR and Johnson folded controller. It firstly encoded the determined test vector to LFSR vector seed, then decoded and rear-ranged the LFSR seed to get a new confirmatory tests vector. The 1SCSA85 experimental results show that the testing pro-gramme improves the correlation of the vector and significantly reduces of test vector the transition, to reduce power consump-tion. This apaper focused on a double-seedeu coding methods and data analysis of results.%为了降低测试功耗,提出一种新的低功耗测试矢量方案,该方案增设了一个可编程的约翰逊计数器.这种技术首先对确定测试矢量进行编码得到LFSR矢量种子,然后对LFSR种子解码、重排得到新的测试矢量.通过ISCAS85实验结果表明,该技术能够改善测试矢量之间的线性相关性,大量减少测试矢量之间的跳变,达到降低功耗的目的.重点介绍了双重编码种子的方法和数据结果分析.

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