基于FPGA的全局异步局部同步四相单轨握手协议实现

摘要

An asynchronous state-holding unit was designed based on LUT. in commercial FPGA, according to this carries out the interface circuit, clock pause circuit of globally asynchronous locally synchronous system, complete 4-phase bundled-data handshake protocol further. Target a technique according to the logic-lock of Quartus, adopt Verilog HDL carry on a behavior description and set up Hazard-free C unit database, at Altera Cyclone II EP2C35F672C6, complete the test of GALS system, result proves effect better.%在常规FPGA中设计了基于LUT的异步状态保持单元,实现了全局异步局部同步系统的接口电路、时钟暂停电路,进一步完成四相单轨握手协议.基于Quartus软件的逻辑锁定技术,采用Verilog HDL进行行为描述,构建了无冒险C单元库.在Altera Cyclone Ⅱ EP2C35F672C6器件上,完成了GALS系统的时序仿真,证明了四相单轨握手的正确性.