在雷达实时仿真系统中,通过匹配滤波法,利用FPGA硬件实现了数字脉冲压缩功能模块.根据仿真系统通用性要求,定义了标准的模块接口界面；依据频域FFT法,设计了流水式并行结构,满足信号的实时输入输出与高速处理,并给出了共享FFT引擎结构,节省近一半资源.为了进一步减少理论误差,引入分段卷积思想,具体设计了重叠相加法电路.实验结果表明,多种方案完成了预期压缩功能,数据吞吐率达到每秒数十兆,处理时间仅约10 μs.%In real-time radar simulation system, a digital pulse compression function module was realized by FPGA, which followed matched-filter rules. According to generality requirements of simulation system, the standard module interface was defined. Using FFT method in frequency domain, pipeline and parallel structure was designed for real-time input and output. Also a structure of shared FFT engine was proposed to save about half resources. In order to decrease theoretical error, segmental convolution was introduced, and overlap-then-add circuit was designed. The results show that, all projects complete the expected function, and could process tens of Mega datum per second with nearly 10 μs delay.
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