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Techniques for Fast, Energy Efficient On-Die Global Communication

机译:快速,节能的片上全局通信技术

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摘要

Communication surpasses computation as the power and performance bottleneck in forthcoming exascale processors. Scaling has made transistors cheap, but on-chip wires have grown more expensive, both in terms of latency as well as energy. Therefore, the need for low energy, high performance interconnects is highly pronounced, especially for long distance communication. In this work, we examine two aspects of the global signaling problem. The first part of the thesis focuses on a high bandwidth asynchronous signaling protocol for long distance communication. Asynchrony among intellectual property (IP) cores on a chip has become necessary in a System on Chip (SoC) environment. Traditional asynchronous handshaking protocol suffers from loss of throughput due to the added latency of sending the acknowledge signal back to the sender. We demonstrate a method that supports end-to-end communication across links with arbitrarily large latency, without limiting the bandwidth, so long as line variation can be reliably controlled. We also evaluate the energy and latency improvements as a result of the design choices made available by this protocol. The use of transmission lines as a physical interconnect medium shows promise for deep submicron technologies. In our evaluations, we notice a lower energy footprint, as well as vastly reduced wire latency for transmission line interconnects. We approach this problem from two sides. Using field solvers, we investigate the physical design choices to determine the optimal way to implement these lines for a given back-end-of-line (BEOL) stack. We also approach the problem from a system designer's viewpoint, looking at ways to optimize the lines for different performance targets. This work analyzes the advantages and pitfalls of implementing asynchronous channel protocols for communication over long distances. Finally, the innovations resulting from this work are applied to a network-on-chip design example and the resulting power-performance benefits are reported.
机译:在即将到来的亿亿级处理器中,通信超越了计算能力和性能瓶颈。缩放使晶体管变得便宜,但就延迟和能量而言,芯片上的导线变得更加昂贵。因此,特别是对于长距离通信,对低能耗,高性能互连的需求非常明显。在这项工作中,我们研究了全局信号问题的两个方面。本文的第一部分集中在用于长距离通信的高带宽异步信令协议上。在片上系统(SoC)环境中,片上知识产权(IP)内核之间的异步已成为必需。传统的异步握手协议由于将确认信号发送回发送方而增加了延迟,因此吞吐量受到损失。我们演示了一种方法,只要可以可靠地控制线路变化,就可以支持跨任意延迟的链路之间的端到端通信,而不会限制带宽。由于该协议提供的设计选择,我们还将评估能量和延迟的改进。传输线作为物理互连介质的使用显示出对深亚微米技术的希望。在我们的评估中,我们发现能耗更低,并且传输线互连的线延迟大大降低。我们从两个方面解决这个问题。使用现场求解器,我们研究了物理设计选择,以确定对于给定的后端(BEOL)堆栈实施这些生产线的最佳方法。我们还从系统设计者的角度解决该问题,寻找优化针对不同性能目标的生产线的方法。这项工作分析了实现异步信道协议进行长距离通信的优点和陷阱。最后,这项工作所产生的创新被应用于片上网络设计实例,并报告了由此带来的功率性能优势。

著录项

  • 作者

    Das, Shomit.;

  • 作者单位

    The University of Utah.;

  • 授予单位 The University of Utah.;
  • 学科 Computer engineering.
  • 学位 Ph.D.
  • 年度 2017
  • 页码 107 p.
  • 总页数 107
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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