Towards Provably Secure Logic Locking for Hardening Hardware Security

摘要

Economic concerns have led to the globalization of the integrated circuit (IC) design flow, and in turn, rendered ICs susceptible to attacks including counterfeiting, intellectual property (IP) piracy through reverse engineering, overbuilding, and hardware Trojans. Many countermeasures including watermarking, IC camouflaging, split manufacturing, and logic locking have been developed to thwart these attacks, with most focusing on specific attack scenarios and lacking formal proofs of security.;Among the proposed countermeasures, logic locking has emerged as a versatile and easy-to-integrate solution that assumes only a designer to be trusted. Logic locking protects a design with a secret key; only upon activation with the correct key, the design is functional. A considerable challenge, however, is that all traditional logic locking techniques are susceptible to powerful SAT attacks that leverage Boolean satisfiability to refine the key search space quickly.;This thesis aims to develop provably-secure and cost-effective logic locking algorithms that offer holistic security against all attacks, can be integrated with the existing EDA tools, and can adapt to the changing business and threat models. The thesis presents theoretical proofs of security as well as the experimental results for the first logic-locked chip fabricated using Global Foundries 65nm LPe technology.