Distributed decap-padded standard cell based on-chip voltage drop compensation framework.

摘要

Technology induced voltage scaling coupled with faster switching, have made the circuit behavior very sensitive to the power supply variations. The effect is classified as power and ground bounce problems. Power and ground bounce can inject random glitches which propagate as mal-functioning logic.;On-chip decoupling capacitors (Decap) are used to reduce the power supply noise. Traditionally, lumped decaps are placed in the chip-finishing stages at available white spaces. However, insufficient budgeting at an early stage and lack of placement estimation have often positioned the decaps at a distance away from the switching nodes. Experimental results show that proximity of the decaps to the violating switching nodes is more effective in power supply noise cancellation. This work attempts to develop an alternative framework to incorporate the decaps in a design close to the switching nodes, thus making them more effective.;The proposed voltage drop optimization framework comprises of three components. First, a special standard cell library with minimum decap padding is developed in order to place decaps closest to the victim nodes. Second, we propose an optimization algorithm to incorporate these standard cells together with minimal value of lumped decaps in the physical synthesis stages. Lastly, we develop an engineering change order placer to generate a valid decap-optimized placement. The developed framework is integrated with the commercial backend design tools (Cadence and Synopsys). The effectiveness of our work has been demonstrated on standard benchmark circuits.