Designs of broadband highly linear CMOS LNAs for multiradio multimode applications.

摘要

With the proliferation of wireless communications, there emerges a trend towards integrating multiple wireless functionalities into one mobile device. Recently we have been observing a paradigm shift in the integrated wireless transceiver design where several narrow-band receivers tailored for dedicated applications, e.g. cellular and wireless LAN (Local Area Network), are replaced by one single circuit which is reconfigured to support different radio standards, the so-called "Universal Receiver". The front-end circuits of the universal receiver therefore have to be able to accommodate operations across a wide range of frequency bands, and different performance requirements for low noise and high linearity. Realizing such universal front-ends, e.g. Low-Noise Amplifier (LNA), with a broadband circuit appears attractive because of the reduced cost realized by area reduction due to sharing the core circuits and package pins. In a "digital" receiver architecture, most of the signal processing is replaced by high-speed samplers and digital circuits, but a broadband LNA is still indispensable in order to relax the stringent performance requirements of the subsequent samplers. In this scenario we are actually running into the classic performance trade-off of analog circuits design among noise, linearity, and broadband impedance match. This research examines the issues associated with the implementation of conventional broadband LNAs, and presents design techniques for combined noise and distortion cancelation to achieve simultaneous low noise and high linearity. Detailed analysis are conducted, and verified experimentally with two integrated circuit prototypes fabricated in 0.13 microm and 65 nm CMOS technologies, respectively.