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A hybrid data prefetching architecture for data-access efficiency.

机译:一种混合数据预取架构,可提高数据访问效率。

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摘要

High-performance computing has crossed the Petaflop mark and has been moving forward to reach the Exaflop range. However, while computing resources are making rapid progress, there is a significant gap between processing capacity and data-access performance. Due to this gap, although processing resources are available, they have to stay idle waiting for data to arrive, which has a severe impact on the overall system performance. In the meantime, applications tend to be more and more data intensive. The data-access delay, not the processor speed, has become the bottleneck of computing, especially for high-performance and high-end computing where performance is keen. There is a great need for research in improving data-access performance.;In this dissertation, we propose to improve data-access efficiency with a Hybrid Adaptive Prefetching architecture and associated innovative data prefetching techniques. The Hybrid Adaptive Prefetching architecture is built upon the memory hierarchy model, the for see engineering choice for masking the gap between computing and data-access speed, and enhances it with a hierarchical prefetching model to further mitigate the performance disparity and improve data-access speed. The fundamental idea behind the proposed solution is utilizing the excessive transistors on chip and available computing capability to build up specialized hardware and software approaches to accelerating data accesses, and thus to achieve a high sustained performance instead of a high peak performance. The Hybrid Adaptive Prefetching architecture reduces data-access latency via two stages, cache-memory stage by leveraging specialized hardware solutions and memory-disk stage by exploiting innovative software solutions. It improves data-access efficiency by harvesting the benefits of comprehensive, aggressive and adaptive prefetching strategies. The goal of this dissertation is to exploit hardware, compiler and system support to provide a systematic solution to boosting data-access performance for high-performance and high-end computing. Extensive experimental testing has been conducted to validate the design and verify the performance gain, and the results have demonstrated significant performance improvement. The Hybrid Adaptive Prefetching architecture can benefit a variety of applications such as scientific simulation, data mining, geographical information system, multimedia and visualization applications, etc. It will have a broad impact on improving data-access efficiency for high-performance and high-end computing.
机译:高性能计算已经超过了Petaflop的标记,并且一直在向前发展以达到Exaflop范围。但是,尽管计算资源正在快速进步,但是处理能力和数据访问性能之间仍然存在巨大差距。由于存在这一差距,尽管处理资源可用,但它们必须保持空闲状态以等待数据到达,这对整体系统性能产生了严重影响。同时,应用程序倾向于越来越密集的数据。数据访问延迟而不是处理器速度已成为计算的瓶颈,特别是对于性能要求很高的高性能和高端计算。在提高数据访问性能方面有很大的研究需求。本文提出了一种使用混合自适应预取体系结构和相关的创新数据预取技术来提高数据访问效率的方法。 Hybrid Adaptive Prefetching体系结构建立在内存层次模型的基础之上,该层次是掩盖计算和数据访问速度之间差距的工程选择,并通过分层预取模型对其进行了增强,以进一步缓解性能差异并提高数据访问速度。提出的解决方案背后的基本思想是利用芯片上过多的晶体管和可用的计算能力来构建专用的硬件和软件方法,以加速数据访问,从而实现高持续性能而不是高峰值性能。混合自适应预取体系结构通过两个阶段来减少数据访问延迟,这两个阶段是通过利用专用硬件解决方案来实现的缓存内存阶段,以及通过利用创新的软件解决方案来实现的存储磁盘阶段。它通过收集全面,积极和自适应的预取策略的好处来提高数据访问效率。本文的目的是利用硬件,编译器和系统支持,为提高高性能和高端计算的数据访问性能提供系统的解决方案。已经进行了广泛的实验测试,以验证设计并验证性能增益,结果证明了性能的显着提高。混合自适应预取体系结构可以使各种应用程序受益,例如科学模拟,数据挖掘,地理信息系统,多媒体和可视化应用程序等。它将对提高高性能和高端数据访问效率产生广泛影响。计算。

著录项

  • 作者

    Chen, Yong.;

  • 作者单位

    Illinois Institute of Technology.;

  • 授予单位 Illinois Institute of Technology.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 144 p.
  • 总页数 144
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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