Since the introduction of theMoore's law in 1965, the integrated circuit industry has successfully managed over 50 years of exponential growth in design complexity and the transistor number has grown from thousands to billions on a single chip. Electronic design automation (EDA) tools are among the biggest factors that keep this growth trend and lead to the developments of cost- and energy- efficient robust electronic circuits and systems.;As technology node continues to scale down, the traditional EDA-based design methodology is challenged from many aspects. Firstly, the growing design complexity results in a significant increase in the computational cost and human labor for conducting thorough design analysis and optimization, both of which are keys to IC design successes. Secondly, the sophisticated underlying physics of advanced technology nodes make the modeling capability of the EDA tools questionable. In fact, most of the failures observed in qualification tests are direct results from such modeling issues, examples include mistuned analog circuits, signal timing errors, reliability problems, and crosstalk. The qualification failures in fabricated chips imply additional rounds of designs, known as design respins and it requires more efficient and reliable EDA tools to design high-yield circuits and systems aiming at the maximum utilization of the new technology and potentially eliminate the need for design respins.;In this work, we demonstrate how machine learning helps to alleviate the bottlenecks mentioned above.We particularly focus on the enhancement of simulation-based methodology for efficient design analysis, modeling, optimization, and yield estimation.;The fundamental idea for incorporating machine learning into the existing simulation based design methodology is to harness the statistical models' capability of extracting information from the limited data set and make fast predictions about unobserved designs as well as accurately quantify the prediction uncertainty. The model can be used either as a direct surrogate of the expensive simulator or as a guide for the design decision-making process.;In this work, we demonstrate the efficacy of the proposed methodology through several circuit and system designs. Examples include the calibration of reliability-related degradations in mixed-signal circuits, fast configurations of the physical design flow, automatic analog circuit optimization and intellectual property (IP) reuse, and yield estimation of SRAM cells with low failure probability.
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