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Two-loop controlled ultra-high frequency DC-DC converter.

机译:两回路控制的超高频DC-DC转换器。

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摘要

In this research, an ultra-high frequency dynamically adaptive power supply targeted for radio frequency PA's is conceived, designed and simulated with a discrete integrated circuit. The research presented in this thesis can be divided into four major contributions to the power management technology: switching frequency of 100 MHz, delay less than 9 ns with high efficiency, very high bandwidth and reduced size of 9000 mum2.;Communication oriented signals have bandwidth in the range of 3-30 MHz. The switching frequency of the converter should be at least two times that of the signal (Nyquist law) for perfect tracking. In this work, a new control strategy along with custom tailored design at transistor level was proposed and implemented. Each of the above mentioned four contributions are functions of each other. This is an optimization problem with a trade off between efficiency and performance. The design process was carried out in different levels.;The design of synchronous converters for ultra high frequency with high efficiency was carried out by considering a non ideal model which can capture the mechanical and thermal stress. The filter elements influence the operation of the converter in dynamic mode, especially due to the energy transfer operation with respect to the reference signal. To solve energy storage issue a monolithic planar inductor suitable for high frequency with proper Q factor was designed. Any available MOSFET in AMI 0.5 mum technology was not a good candidate due to the resistance and intrinsic capacitance. An equation was derived for maximizing the efficiency of the switches as a function of channel width for a given length of 0.5 mum.;Small signal analysis was carried out and the stability of the system was verified. Analysis leads to the necessity of having a controller for both input and load variations. Two-loop controller was proposed for the system to overcome any transients from the input and load side. A novel controller with inner loop of one cycle controller and an outer loop with a lead compensator was modeled and simulated. Because of the slew rate and bandwidth limitations conventional operational amplifiers resulted in very poor performance. This leads to the development of the controller based on current conveyor and high speed voltage comparator. The proposed current conveyor is the novel one with very high efficiency, excellent bandwidth of 10 GHz and deprived of saturation. A new voltage comparator is proposed for high speed operation.;An integrated circuit for decoupling the gate signal into two non overlapping signals for converter was designed. A driver circuit was incorporated along with the adaptive delay circuit to drive the switches of the synchronous converter with required gate power. Total area occupied by the controler is 6000 mum 2. The outer loop was designed with current conveyors to constitute a PI controller.;The designed controlled converter now operates at desired RF levels, with power consumption being as low as 45% of that of the systems that are currently in use. The controller design has been completed on 0.5 micron technology, using the AMI Semiconductor technology. The entire chip occupied 0.009 mm2 with one third going for the converter part. The layout will be sent for fabrication to MOSIS and testing of the results would follow thereafter. Current outer loop will be replaced by a TYPE-III amplifier which will provide a more robust operation.;Applications of the controlled converter have been discussed with respect to Handheld Wireless Devices and various inputs that can qualify for power management. The chip is so designed that it can accommodate these inputs in order to provide more effective feedback to the system and thus provide power at the threshold level when required, thereby prolonging the battery life. The chip is expected to increase the life of the battery at least 4 times longer than the fixed controlled system or two times compared to the dynamic converter operating with conventional PWM control.
机译:在这项研究中,针对射频PA的超高频动态自适应电源是通过分立集成电路来设计,设计和仿真的。本文对电源管理技术的研究可分为四大方面:开关频率为100 MHz,延迟小于9 ns,效率高,带宽极高,减小了9000 mum2的尺寸;面向通信的信号具有带宽在3-30 MHz的范围内。转换器的开关频率应至少为信号开关频率的两倍(奈奎斯特定律),以实现完美跟踪。在这项工作中,提出并实施了一种新的控制策略以及晶体管级的定制设计。上述四个贡献中的每一个都是彼此的功能。这是一个优化问题,需要在效率和性能之间进行权衡。设计过程是在不同的层次上进行的。通过考虑一个可以捕捉机械应力和热应力的非理想模型,进行了超高频高效同步转换器的设计。滤波器元件在动态模式下影响转换器的操作,尤其是由于相对于参考信号的能量传输操作。为了解决能量存储问题,设计了一种适用于具有适当Q因子的高频的单片平面电感器。由于电阻和固有电容,AMI 0.5 mum技术中任何可用的MOSFET都不是很好的选择。对于给定的0.5μm的长度,导出了一个方程,以使开关的效率最大化,该效率是通道宽度的函数。进行了小信号分析,并验证了系统的稳定性。分析导致必须有一个用于输入和负载变化的控制器。提出了针对该系统的两环控制器,以克服来自输入端和负载端的任何瞬变。对一个具有一个周期控制器的内环和一个带有超前补偿器的外环的新型控制器进行了建模和仿真。由于压摆率和带宽限制,常规运算放大器导致非常差的性能。这导致了基于电流传送器和高速电压比较器的控制器的发展。提出的电流传送器是一种新型的传送器,具有很高的效率,10 GHz的出色带宽和不饱和的特性。提出了一种用于高速工作的新型电压比较器。设计了一种将门信号解耦为两个非重叠信号以供转换器使用的集成电路。驱动器电路与自适应延迟电路结合在一起,以所需的栅极功率驱动同步转换器的开关。该控制器占用的总面积为6000 mum2。外部环路采用电流传输器进行设计,以构成PI控制器。;现在,所设计的受控转换器可在所需的RF电平下工作,功耗低至PI控制器的45%。当前正在使用的系统。使用AMI半导体技术的控制器设计已经完成于0.5微米技术。整个芯片占0.009平方毫米,三分之一用于转换器部分。该版图将发送给MOSIS制造,然后进行结果测试。当前的外部环路将由TYPE-III放大器代替,该放大器将提供更稳定的操作。受控转换器的应用已针对手持无线设备和各种符合电源管理要求的输入进行了讨论。该芯片的设计使其可以容纳这些输入,以便向系统提供更有效的反馈,从而在需要时以阈值水平提供功率,从而延长了电池寿命。与采用传统PWM控制的动态转换器相比,该芯片有望将电池的使用寿命延长至少4倍,比固定控制系统长2倍,或将电池寿命延长2倍。

著录项

  • 作者

    Suresh, Sindhu.;

  • 作者单位

    Polytechnic Institute of New York University.;

  • 授予单位 Polytechnic Institute of New York University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 162 p.
  • 总页数 162
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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