Enabling dynamic voltage and frequency scaling in multicore architectures.

摘要

Traditionally, application speedup was the primary goal for processor designers. To this end, for many years, designers continuously deployed architecture techniques to increase the processor frequency such as pipelining, cache memory, and out-of-order superscalar execution. However, high clock frequency no longer dictates the system goals which now include power consumption and energy efficiency. Since design modifications to address power consumption generally limit processor performance and reduce peak operating frequency, operating systems are key to controlling the voltage level and frequency of a machine during execution. To date, operating system methodologies in controlling the voltage and frequency configuration of the machine are mostly based on ad-hoc means, thermal emergencies or constraining the power consumption of the system. Moreover, such operating system techniques have mostly been investigated for single-core, not multicore processors. Likewise, such support for multicores typically used simulators that do not have true constraints such as transition time to change frequency, variation in memory latency, cache hierarchy and design, scheduling quanta, full execution of large workloads, variation in system availability and finally but not the least Input/Output operations such as disk reads.;This thesis presents a scheduling methodology for multicore processors which maps running applications to cores executing at varied clock speeds based on their runtime performance characteristic. Two schemes of mapping tasks to cores are designed. An asynchronously run power optimizer is devised to adapt to the needs of the current workload in terms of core clock speed on a multicore system accomplished by utilizing the information provided by the scheduler about the needs of the current workload. The entire system is implemented as a module for the Linux kernel.;In addition to these contributions, this thesis performs an extensive analysis on the system for six selected workloads to analyze the effects on performance, power and energy efficiency. Overall, this thesis presents an evaluation of a potential infrastructure that may aid compiler and user-space runtime designers to utilize the framework and provide useful information about task characteristic and phase behavior to the operating system scheduler for better task to clock speed assignments.