Characterizing, modeling and mitigating microarchitecture vulnerability and variability in light of small-scale processing technology.

摘要

The rapidly increased soft error rate (SER) due to the scaled processing technology is one of the critical reliability concerns in current processor design. In order to characterize and mitigate the microarchitecture soft-error vulnerability in modern superscalar and multithreaded processors, I developed Sim-SODA (Software Dependability Analysis), a unified framework for estimating microprocessor reliability in the presence of soft errors at the architectural level. By using Sim-SODA, I observed that a single performance metric is not a good indicator for program vulnerability; on the other hand, a combination of several performance metrics can well predict the architecture-level soft-error vulnerability. Based on the observation that issue queue (IQ) is a reliability hot-spot on Simultaneous Multithreaded (SMT) processors, I proposed VISA (Vulnerable InStruction Aware) Issue and ORBIT (Operand Readiness Based InsTruction) dispatch to improve the IQ reliability. I further combined the circuit and microarchitecture techniques in soft error robustness on SMT processors to leverage the advantage of the two levels' techniques while overcoming the disadvantage of both. Results show that my proposed techniques have strong ability in improve IQ reliability with negligible performance penalty.;As one of the nano-scale design challenges, process variation (PV) significantly affects chip performance and power. I characterized the microarchitecture soft error vulnerability in the presence of PV, and proposed two techniques that work at fine-grain and coarse-grain levels to mitigate the impact of PV mitigation techniques on reliability and maintain optimal vulnerability, performance, and power trade-offs. Negative Body Temperature Instability (NBTI) has become another important reliability concern as processing technology scaled down. Observing that PV has both positive and negative effects on circuits, I took advantage of the positive effects in NBTI tolerant microarchitecture design to efficiently mitigate the detrimental impact of PV and NBTI simultaneously. The trend towards multi-/many-core design has made network-on-chip (NoC) a crucial hardware component of future microprocessors. I proposed several techniques that hierarchically mitigate the PV and NBTI effect on NoC while leveraging their benign interplay.