Design techniques for video speed analog-to-digital converters.

摘要

The focus of this thesis is high-speed high-resolution pipeline analog-to-digital converters in a CMOS process. First, R-C based successive-approximation analog-to-digital converters, that can be pipelined while preserving speed, are investigated. Two new structures, for eight and ten bit converters, are developed. The advantage of the new architectures over existing systems is that they require less area and can achieve almost ideal pipeline conversion rate. The fabricated converters achieved conversion rates of 1.3 MS/s and 0.8 MS/s, respectively.;To achieve high-resolution high-speed conversion in a video-speed converter (10-bit, 25-30 MHz), a high-resolution comparator was designed. The fabricated comparator resolves a quarter of 1 mV (including residue of offset) at a rate of 30 MS/s. To reduce power and save area, digital error correction algorithms, that can take advantage of limited resolution and bounded offset of simple comparators, were presented. They are based on a general error-correction theory which offers a general method to minimize the analog hardware as well as digital error-correction circuitry. Substantial reduction in the amount of hardware can be achieved in comparison to previously reported work.;To achieve a substantial improvement in A/D converter, a new type of internal D/A converter is introduced. The internal converter is based on a new scalable input differential pair whose transconductance is independent of its common-mode voltage. For that reason the differential pair was also used in the design of the sample-and-hold amplifier. This greatly enhanced the linearity of the sample-and-hold stage. The thesis provides a detailed linearity analysis of the conventional and the new differential pairs. It also presents closed form simple equations for harmonic distortion in a folded cascode op-amp as well as design equations for the newly introduced D/A converter. The measurement results of the fabricated subranging stage and the sample-and-hold amplifier confirmed the accuracy of the analyses and simulation results. The accuracy of the internal converter was better than 12 bits over a 1.6 V range. The important feature of the new internal D/A converter is that it requires no capacitors, thus allowing high-resolution A/D converters be implemented in a digital CMOS process next to a DSP system.