A DSP-56001 software architecture for a radio and data packet controller.

摘要

The Advanced Radio and Data Packet Controller (ARDPC) is a prototype second generation radio and data packet controller for mobile data communications which is capable of full duplex 4800 bps operation using FM modulated bipolar waveforms and the Radio Network Communications Protocol (RNCP) signalling scheme. The ARDPC is implemented using a duo processor hardware/software architecture featuring a Motorola DSP-56001 digital signal processing (DSP) chip teamed with a Motorola 68000 microprocessor. The ARDPC represents an advancement in radio and data packet controller design through the use of DSP in its modem functions. This design feature allows the ARDPC to offer much improved intelligence, flexibility and functionality over its non-DSP predecessors. One notable functional improvement is the ability to perform message processing at the controller level to support radio channel monitoring operations.;This report focuses on the DSP-56001 software requirements, architecture, and DSP algorithms implemented for the ARDPC. The description of the software architecture is presented using a top-down module decomposition employing data and control flow (dcf) diagrams as tools. The DSP algorithms described include the modulation, demodulation and data detection algorithms for the ARDPC modem. The performance of these algorithms is measured using static and fading bit-error rate (BER) performance, modulation spectral occupancy and processor bandwidth utilization. The demodulator BER performance is measured against white Gaussian noise and is shown to be 2-3 dB better than a first generation controller. Spectral occupancy measurements of the ARDPC modulation scheme is shown to easily meet Federal Communications Commission (FCC) requirements for 25 kHz UHF/VHF radio channels while processor bandwidth measurements confirm that the software architecture is fully capable of supporting 4800 bps data communication.