Advanced computational capability requires increased electronic signal speed. This requirement is forcing the electronics industry to design miniaturized, highly integrated, high-density packaging of electronic components, all of which lead to increased component junction temperatures and energy dissipation rates at the chip, module, and system levels. Chip power density is projected to exceed 100W/cm;The current research is divided into three phases. The work conducted in Phases 1 and 2 focuses on the enhancement of pool boiling heat transfer via surface treatments and "gassy" sub-cooling. In Phase 3, quantification of the bubble departure parameters as a function of heat flux is investigated.;Four benign methods of generating surface micro-structures which provide heat transfer enhancement are developed and over twenty enhanced surfaces are investigated. Pool boiling results from enhanced, horizontally oriented, rectangular surfaces immersed in saturated FC-72, indicate wall superheat reductions (70 to 85%) and up to a 109% increase in the critical heat flux. In Phase 2, sub-cooling is used in conjunction with surface treatments to provide further enhancement. The effects of sub-cooling and dissolved gas concentration on wall superheats and the critical heat flux are quantified. Two surface micro-structures are applied to a silicon test chip and tested at saturated and sub-cooled conditions. Heat dissipation rates of ;Understanding the heat transfer mechanisms involved during nucleate boiling requires quantitative knowledge of the bubble departure size and frequency. A technique is developed using Laser Doppler Anemometry (LDA) which measures the instantaneous and time-averaged single-site bubble departure frequency. Bubble size, departure frequency, and rise velocity from an 80
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