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Production planning and scheduling for semiconductor device testing.

机译:半导体器件测试的生产计划和计划。

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摘要

In this dissertation the semiconductor device testing process is analyzed and modeled. The goal is to accurately model the capacity of the final test stage of semiconductor manufacturing for long-term planning models, and to find good short-term scheduling strategies for this complex production environment. Better scheduling methods increase the throughput of the facility, as well as provide data to increase the accuracy of long-term planning. The information on the arriving product mixes, the scheduling principles, and statistics of rate efficiencies of test heads can be fed back to the planning system to create an accurate capacity model of the test facility that can be used to plan its production and to evaluate its performance.; This is the first attempt to capture all the complexities of the shared-CPU semiconductor testing environment, and to model a large variety of testing environments for scheduling purposes. Several simplified versions of the test-floor scheduling problem are identified as well-known combinatorial optimization models. The general test-floor scheduling problem is then formulated and a computerized enumeration program is developed for determining the highest value schedule. The state-space representation of the semiconductor test operations captures the unique structure and characteristics of the semiconductor device test equipment.; The enumeration program proposed herein serves as a benchmark, generating optimal solutions against which heuristics may be compared. It also serves as a platform for developing heuristics. Various rules may be devised to restrict consideration of unpromising nodes in the state-space, thereby speeding up the algorithm's execution.; Both the capacity modeling problem and the test scheduling problem are characterized by theoretical complexity, thus finding good solutions for them has theoretical value. The suggested models can be used to solve planning and scheduling problems arising in a variety of production environments, ranging from small ASICs manufacturing firms to large, mass production type companies.
机译:本文对半导体器件测试过程进行了分析和建模。目的是为长期计划模型准确地建模半导体制造的最终测试阶段的能力,并为这种复杂的生产环境找到良好的短期计划策略。更好的调度方法可以提高设施的吞吐量,并提供数据以提高长期计划的准确性。有关到达的产品组合,调度原理和测试头效率的统计信息可以反馈到计划系统,以创建测试设施的准确容量模型,该模型可以用于计划其生产和评估其生产能力。性能。;这是捕获共享CPU半导体测试环境的所有复杂性并为调度目的建模各种测试环境的首次尝试。测试楼层调度问题的几种简化版本被识别为众所周知的组合优化模型。然后制定一般的测试地板调度问题,并开发一个计算机枚举程序来确定最高价值调度。半导体测试操作的状态空间表示捕获了半导体器件测试设备的独特结构和特性。本文提出的枚举程序用作基准,生成可以与启发式进行比较的最佳解决方案。它还用作开发启发式的平台。可以设计各种规则来限制对状态空间中无用节点的考虑,从而加快算法的执行。能力建模问题和测试调度问题都具有理论上的复杂性,因此为它们寻找良好的解决方案具有理论价值。所建议的模型可用于解决各种生产环境中产生的计划和调度问题,从小型ASIC制造公司到大型批量生产型公司不等。

著录项

  • 作者

    Carmon, Tali Fried.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Industrial.; Operations Research.; Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1995
  • 页码 200 p.
  • 总页数 200
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 一般工业技术;运筹学;无线电电子学、电信技术;
  • 关键词

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