Logic-level timing analysis for digital integrated circuits.

摘要

Timing analysis is an essential step in the process of designing, optimizing, and testing integrated circuits. One of the most valuable pieces of information available from timing analysis is the answer to whether a circuit design will operate correctly at a designated speed. For this purpose, the longest propagation delay of the circuit must be less than the system clock cycle. Traditional timing analysis, such as the static timing approach, uses the longest path delay of a circuit as an estimate of the circuit delay. Unfortunately, the longest path is often an unsensitizable path, and this causes static timing analyzers to overestimate the circuit delay. This is not acceptable for the aggressive design strategies of today. Due to the popular use of logic synthesis and modular design, circuits with long false paths are becoming more common.; In this dissertation, the problem of finding the longest sensitizable path and its delay for a digital circuit from its logic-level description is studied. Factors that affect the accuracy and the performance of timing analysis are first identified, and effective solutions are proposed. A powerful ATPG-based (Automatic Test Pattern Generation) path sensitizability analysis technique is developed. To cope with the potentially exponential number of paths in the search space, a path search algorithm is developed and combined with the path sensitization technique to eliminate a significantly large number of false paths without explicit enumeration or path sensitizability analysis. A proof-of-concept timing analysis system is implemented, and the performance is demonstrated through the experimental results on some combinational benchmark circuits.