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LNA and mixer design study for 900 MHz receiver applications.

机译:针对900 MHz接收器应用的LNA和混频器设计研究。

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摘要

The implementation of a radio frequency front end receiver operating in the 900 MHz band is explored in this thesis. The low noise amplifier (LNA) and mixer are designed using an advanced silicon bipolar process in which monolithic inductors and baluns are to be made available.; The emphasis of the LNA design was placed on achieving a minimal power consumption while satisfying the desired performance. A cascode and common-emitter configuration for the LNA are explored. The information presented should be sufficient to easily modify the design to achieve a desired performance. An existing mixer, intended for 1.9 GHz operation and implemented in 0.8 {dollar}mu{dollar}m BiCMOS technology was measured and simulated. The design was modified for 900 MHz operation using the advanced 0.5 {dollar}mu{dollar}m silicon bipolar process.; At a supply voltage of 1.0 V, the common-emitter LNA has a power dissipation of 4 mW and third-order input intercept of {dollar}-{dollar}5.5 dBm, with a 1.27 dB noise figure and 13.9 dB gain. The cascode LNA has an input intercept of {dollar}-{dollar}5.6 dBm with a noise figure of 1.43 dB and 14.8 dB gain. At a supply voltage of 1.9V, the power dissipation of the cascode LNA is less than 6 mW. The 0.8 {dollar}mu{dollar}m double-balanced mixer was measured to provide a conversion gain of 7.9 dB with a third order input intercept of {dollar}-{dollar}3.6 dBm and single-sideband noise figure of 14.3 dB. Power dissipated is less than 25 mW at a supply voltage of 3V. In the advanced process technology, a double-balanced mixer gave an input intercept of +2.6 dBm with a 9.7 dB single-sideband noise figure and +3.4 dB power conversion gain. Power dissipated by this mixer is less than 18 mW at a supply voltage of 3V. (Abstract shortened by UMI.)
机译:本文探讨了在900 MHz频段工作的射频前端接收机的实现。低噪声放大器(LNA)和混频器采用先进的硅双极工艺设计,其中将提供单片电感器和巴伦。 LNA设计的重点是在满足所需性能的同时实现最低功耗。探索了用于LNA的级联和共发射极配置。所提供的信息应足以轻松修改设计以获得所需的性能。测量并模拟了现有的混频器,该混频器旨在以1.9 GHz的频率运行并采用0.8 um BiCMOS技术实现。使用先进的0.5μm硅双极工艺对设计进行了900 MHz的工作修改。在1.0 V的电源电压下,共发射极LNA的功耗为4 mW,三阶输入截距为{dollar}-{dollar} 5.5 dBm,噪声系数为1.27 dB,增益为13.9 dB。级联LNA的输入截距为{dollar}-{dollar} 5.6 dBm,噪声系数为1.43 dB,增益为14.8 dB。在1.9V的电源电压下,级联LNA的功耗小于6 mW。测量了0.8μm的双平衡混频器,可提供7.9 dB的转换增益,三阶输入截距为{-} 3.6 dBm,单边带噪声系数为14.3 dB。在3V的电源电压下,功耗低于25 mW。在先进的处理技术中,双平衡混频器的输入截距为+2.6 dBm,单边带噪声系数为9.7 dB,功率转换增益为+3.4 dB。在3V的电源电压下,此混频器消耗的功率小于18 mW。 (摘要由UMI缩短。)

著录项

  • 作者单位

    Carleton University (Canada).;

  • 授予单位 Carleton University (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.Eng.
  • 年度 1996
  • 页码 171 p.
  • 总页数 171
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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