Wideband spread-spectrum digital communications for portable applications.

摘要

This thesis addresses the design and implementation of an indoor wireless system to support multimedia communication, with emphasis on a broadband downlink capable of supporting digital video. In particular, the development of integrated analog RF front-end and baseband digital interface circuitry, as well as the system simulations driving the design, have been examined. An ultimate per-user data rate 2 Mbps is the target; to achieve the required capacity, a picocellular system architecture will be employed, using cells on the order of 5m in size.; In examining multiple access strategies for such an application, direct-sequence spread-spectrum, or code-division multiple access, possesses many advantages. For this system, a symbol rate of 1 Mbaud with a chipping rate of 64 Mchip/sec is used; for the spreading code, a Walsh-PN hybrid loosely based on the existing IS-95 digital cellular standard is chosen. Beyond providing multiple access, the ability to resolve multiple arrivals and detect adjacent channels in the digital baseband circuitry also affords many benefits that other systems, such as time-division or frequency-hop, cannot easily provide. Taking advantage of the broadcast mode transmission of the downlink, each cell is keyed to a pseudorandom pilot tone, which tremendously simplifies timing recovery and detection in the mobile.; Lastly, the implementation of a high-performance, monolithic RF transceiver has been addressed. It is evident that an all-MOS RF system operating in the 1-2 GHz range is quite feasible, given technologies that are currently available. The benefits of integration are enormous: reduced parasitic effects, greater manufacturability, and minimized power requirements to drive off-chip loads. Likewise, by examining the basic architecture used in the transceiver, the underlying digital nature of the signal can be used to simplify the resulting circuit considerably: homodyne demodulation using passive sampling techniques is one important example of how this can be achieved. By taking advantage of these techniques, factors of 10-20x reduction in the power consumed by the analog RF circuitry in conventional designs can be achieved, at the expense of increased digital process. In some sense, the analog front-end has been reduced to its most basic functionality: amplification, filtering, frequency conversion, and analog-to-digital conversion.; Lastly, by exploiting dedicated parallel and pipelined techniques, a low-power spread-spectrum receiver has been designed in spite of the tremendous chipping rate of the system (64 Mchip/sec). By scaling the supply voltage, and employing multiple supplies into the chip, optimal voltages can be chosen to meet throughput requirements and minimize power consumption in the baseband digital logic. A prototype receiver has been developed; due to technology limitations, data rate is limited to 32 Mchip/sec; total power consumption of the prototype, implemented as a two custom ASIC solution, is 154 mW. (Abstract shortened by UMI.)