Quadratic programming based framework for high-level area estimation and performance-driven placement for asics.

摘要

The work presented here explores the application of quadratic programming based optimization techniques to two major areas of VLSI CAD domain namely, (i) performance driven placement and (ii) area estimation after high-level synthesis. The quadratic programming technique is a very fast method and it also results in high quality solutions.; With the increasing complexity of present-day integrated circuits, there is a need for fast layout generation algorithms that are driven by performance constraints such as timing and clocking. We model the placement problem as a quadratic optimization problem and suggest techniques for incorporating the performance constraints. The performance constraints that we consider for the placement problem are timing and clocking. The timing driven placement computes the net delay bounds and guides the placement problem under the timing constraints. Also, techniques for minimizing the critical path delay have been incorporated into the model. The clock-skew minimization problem attempts to generate a zero-skew routing for the clock signal while minimizing performance costs. While addressing the clock-skew minimization problem, a new clock-routing tree has been proposed which is well suited for routing the clock signal in row-based design styles.; One of the main objectives of placement algorithms is to minimize the overall area of an IC chip. The overall area depends on the logic module area as well as the wiring area. The latter can be found exactly after completion of routing. Thus placement algorithms can only estimate the routing cost. As part of this research we study the validity of the metrics used for the estimation of quality of placement.; The layout area estimation problem is addressed by first computing a Quadratic Programming based floorplan for the given RTL design. The resulting floorplan is then processed through a topological floorplanner to minimize the layout area. The area estimates are then computed using Steiner tree based routing estimation heuristics.; All of the above techniques have been tested on a number of benchmark examples and the experimental results confirm the effectiveness of the proposed techniques.