Design and test of high-performance analog-to-digital converter based on subranging architecture.

摘要

Complete digital signal processing requires analog circuits acting as interfaces between the digital system and the outside world, which is mostly analog. The analog-to-digital (A/D) converter plays a significant role as an interface between the physical world and digital systems.;Accuracy, speed and power dissipation are the main performance criteria for high speed analog-to-digital converters. These criteria depend on design techniques, architecture and mode of operation. A/D converters with a pipelined architecture and using switched-capacitance techniques are dominant in high performance analog-to-digital converters. However, the sample and hold delay between stages limits its speed. In addition, the technology used for switched-capacitor circuits is not compatible with standard digital process technology and their performances degrade at low voltage operation.;To overcome these limitations, a new architecture for A/D converters using some new design techniques has been explored in voltage mode. In this architecture, the conversion speed is improved by parallel subtraction and comparison. The subcircuits of this architecture have been designed in 0.8 mum BiCMOS technology. These subcircuits form a 3-bit converter followed by an 8-bit standard converter, which performs as an 11-bit analog-to-digital converter. In our first implementation, the A/D converter operates at 5 Volts and shows a signal-to-noise ratio of 62 dB at 1 MHz input frequency. The non-linearity errors, INL and DNL, are less than 1 LSB in the 11-bit A/D converter.;In addition, the low voltage and low power dissipation of current mode circuits motivated us to develop and explore the new architecture in current mode. In order to design the current mode analog-to-digital converter, the current mirror, a fundamental circuit in current mode, has been modeled as a current mode switch. In this way, all the parameters of normal switches have been developed in a current mode switch. A novel current mode switch has been implemented in 1.2 mum CMOS MITEL technology. The test results show that the performance of current mode switches can be better than those of voltage mode switches for some applications. The low insertion loss of 0.7 dB at 300 MHz could make it a good candidate for a current mode A/D converter. A 12-bit high performance A/D converter has therefore been designed by applying current mode switch in a new A/D converter architecture. However, this 3-Volt converter shows INL and DNL non-linearity errors of 1.5 and 1 LSB respectively. In addition, the designed A/D has a 60 dB signal-to-noise ratio with 100 KHz input which shows 10 to 11 bits as the effective number of bits. The effective number of bits decreases to 9 when the input frequency increases to 50 MHz.;Finally, a new digital test approach has been investigated. A digital BIST has been designed and applied for a pipelined A/D converter. This BIST is capable of extracting in the digital domainA/D parameters such as DNL, INL, and offset errors. Applying a test in the digital domain increases test accuracy. In addition, the proposed BIST makes it possible to avoid calibration, which in turn reduces the area overhead.