Frequency translating bandpass sigma-delta modulation for analog-to-digital conversion

摘要

Bandpass Sigma-Delta analog-to-digital (A/D) converters have shown great potential for digitizing intermediate frequency (IF) signals in wireless communication systems. Current implementations of bandpass Sigma-Delta modulators include discrete-time (DT) circuitry using switched-capacitor or switched-current techniques and conventional continuous-time (CT) realization. When the IF frequency is pushed to 70 MHz and above as in cellular phone systems, the DT implementation suffers from the distortion of the front-end sampling circuit; while in the CT implementation, the center frequency accuracy and high-Q requirements of the CT bandpass filter are difficult to achieve. Both DT and CT implementations suffer from clock jitter effect while CT realization is more susceptible to clock jitter in the feedback DAC.;Use of frequency translation inside the Sigma-Delta loop and mixed CT/DT design are presented in this thesis which potentially provide a better solution for high-speed bandpass Sigma-Delta modulation.;The first two chapters provide the background and overview of conventional bandpass Sigma-Delta converters. The third chapter depicts the new theory of frequency translating bandpass Sigma-Delta modulator. Chapter four is an investigation on the clock jitter effect on the performance of bandpass Sigma-Delta modulators. Chapters five and six demonstrate the design, implementation and experimental results of a 400 MHz direct-conversion bandpass Sigma-Delta modulator using MOSIS 3.3V 0.35 mum single-poly, four-metal CMOS process. This modulator achieves 54 dB peak SNR for a 200 kHz (GSM) signal band centered at 100 MHz. Chapter seven concludes this thesis.