A study of on-state conduction in the silicon carbide power DIMOS device.

摘要

SiC is a wide bandgap semiconductor with thermal conductivities and breakdown field strength significantly higher than in silicon. These superior material properties translate into much improved power switching device performance at elevated temperature and power levels. However, the potential of this material is yet to be fully exploited due to immature processing technology.; This dissertation is concerned with the development of a low thermal budget process technology for the fabrication of the SiC power DIMOS (Double Implanted MOSFET). The process sequence is aimed at obtaining improved conduction in the on-state of the DIMOS device. The use of aluminum as the p-well dopant in the SiC DIMOS is shown to be beneficial to improving the on-state conduction through the minimization of step-bunching. Performance comparisons for the DIMOS on 4H and 6H-SiC indicate that the surface of implanted SiC is the cause for the degraded conduction in these devices. The surface disorder is higher in the 4H-SiC polytype than in 6H-SiC.; The specific on-resistance, $Ron,sp$, has been characterized and modeled in the case of the 6H-SiC DIMOS devices. An $Ron,sp$ of 42 m$W$-cm2 has been measured on our DIMOS $Lch=2mm,CellPitch=32mm$ devices which received nitrogen “spacer” implants to help eliminate the JFET pinch resistance. The $Ron,sp$ values for all the devices exhibit a positive temperature coefficient thereby making the devices suitable for paralleling for high current applications.; The dissertation also deals with the modeling of carrier transport at the surface of implanted SiC in order to explain the rounded $ID-VGS$ characteristic and the stretched out transconductance observed in SiC devices on implanted regions. A model based on the existence of bandtail states, which originate from the native disorder on SiC surfaces, is developed to account for the MOSFET conduction behavior on SiC implanted surfaces.; In conventional MOS theory, the electric field influence on the inversion charge is derived neglecting the effect of the interface trapped charge. However, the model developed in this dissertation indicates a lowering of the effective vertical field experienced by the inversion layer electrons in the presence of a large amount of interface trapped charge in bandtail states. The model successfully explains the relative insensitivity of the ‘apparent’ surface mobility to gate bias observed in the ion-implanted SiC MOSFETs.; Numerical simulations are used to illustrate the various effects that a bandtail state distribution has on the MOSFET conduction characteristics. The model is then used successfully to fit the observed experimental data with a characteristic bandtail decay energy parameter of 100 meV for inversion mode devices in 6H-SiC. A modified mobility extraction technique using lateral MOSFETs with varying channel lengths, which can take into account gate voltage dependent series resistances, has been developed to extract ‘apparent’ surface mobilities on SiC at various gate biases and temperatures. We have measured gate bias independent room temperature mobility values around 50 cm2/Vs for inversion mode 6H-SiC devices for a substrate doping of 5 × 1016 cm−3, representing almost an order of magnitude higher values when compared to 4H-SiC. A strong correlation, predicted by our model, is indeed observed between the observed surface mobilities and the effective threshold voltages.