Convolutional coding and Viterbi decoding offer a powerful FEC (Forward-Error-Correction) channel coding scheme widely used in digital communication systems. Examples are space, satellite, and terrestrial wireless communications, where high channel noise levels demand high error-correcting capability. The Viterbi decoder is a central component in the communication receiver, and its design greatly affects the system performance. Computational requirements are excessive even for systems with modest coding performance, and power dissipation becomes a serious concern for wireless applications.; This work explores the use of analog very large scale integration (VLSI), with superior power and area efficiency over digital alternatives, for high-performance portable applications of digital decoding systems. I demonstrate the feasibility of analog Viterbi decoding for long constraint-length convolutional codes by implementing the first K = 7 (64-state) parallel Viterbi decoder with analog Add-Compare-Select (ACS) unit in VLSI. Experimental results demonstrate the area and power efficiency of the approach.; In addition to VLSI implementation, I also address issues concerning theoretical analysis of analog decoding, and provided a mathematical basis for performance analysis and simulation of analog VLSI Viterbi decoders. In particular, I show that ideal analog Viterbi decoding offers superior coding performance over binary hard-decision and digital soft-decision Viterbi decoding, owing to quantization. The model also quantifies effects of imprecision in the analog VLSI implementation, and demonstrates that in practice analog VLSI easily outperforms a 3-bit soft-decision digital implementation.; I extend these analog decoding principles to the design of analog-digital interfaces for high-performance data conversion, and present architectures for high-speed and high-resolution analog-to-digital conversion.
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