MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grained granularity, dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently under testing. It was fabricated using 0.35mum technology and it is targeted to operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors and other contemporary reconfigurable systems. The CAD tools, physical layout design methodology and chip testing of M1 system are outlined. This dissertation presents two extensions of the original MorphoSys architecture as the research directions in the near future. The first extension is to enhance the current MorphoSys architecture into the next generation MorphoSys M2 architecture. The second extension is to make the MorphoSys architecture scalable, leading to the Meta-MorphoSys system. In the Meta-MorphoSys system implementation, a single die would integrate multiple MorphoSys-like units (called Morpho Units) in order to satisfy performance requirements. The preliminary architecture and some discussions on the task partitioning and scheduling of Meta-MorphoSys are presented as well.
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