System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip architectures.

摘要

In this work, we give an approach for making embedded systems execute faster while consuming less power. Our work focuses on embedded system application that are mapped on parameterized system-on-a-chip (SOC) architectures. Tuning the parameters of an SOC can have a large impact on performance and power consumption of an application running on that SOC architecture. A problem with parameterized SOC architectures is the exponential size of their parameter space, making optimal parameter selection a difficult tasks. In this work, we propose a framework for fast and accurate power and performance simulation along with an efficient algorithm for finding Pareto-optimal configurations, namely a set of configurations representing the range of meaningful power and performance tradeoffs obtainable by tuning a parameterized SOC architecture for a specific embedded system application.