Hardware support for quality-of-service guarantees in packet switched networks.

摘要

Modern integrated networks can support the diverse quality-of-service requirements of current and emerging applications by incorporating effective traffic shaping and link scheduling mechanisms. However, processing a large number of packets on a high-speed link requires an efficient hardware implementation of the shaping and scheduling mechanism. This thesis presents new hardware architectures which provide fast, flexible, and efficient implementations for delivering QoS guarantees.; Priority queues are essential in all traffic shaping and link scheduling algorithms, and their efficacy is dependent on an effective priority queue mechanism. We propose two new priority queue architectures that scale to the large number of packets and large number of priority levels necessary in modern switch designs.; Building on these results, we propose two new traffic shaper and link scheduler architectures. By incorporating our programmable shaping and scheduling processor, we propose a complete traffic shaper and link scheduler implementation which achieves high performance and maximum flexibility needed to implement a wide range and mix of shaping and scheduling algorithms. We also investigate traffic shaping and link scheduling issues on an end-host server, and propose a network interface architecture with dedicated shaping and scheduling support.; Finally, we describe a hardware-software codesign and co-simulation tool which we developed to implement our architectures. The tool allowed us to evaluate both low-level hardware and high-level software components of a design using a common platform.; Incorporating event-driven simulation, software performance estimation, and compiled simulation techniques, we were able to easily evaluate different software/hardware partitioning strategies.