Global interconnect modeling for a gigascale system-on-a-chip (GSoC).

摘要

Global interconnects are commonly considered a key potential bottleneck to the advancing performance of future integrated systems. The complete global interconnect architecture of a digital system implemented on a single chip consists of signal, clock, and power-supply distribution networks. Since the signal, clock, and power-supply networks utilize the same interconnect stacks, it is imperative to integrate the complete interconnect architecture to design and optimize global interconnects for a gigascale system-on-a-chip (GSoC).; The objective of this dissertation is to provide a technique for the design and optimization of global interconnect networks in an integrated architecture for global signal, clock, and power-supply networks. To enhance the understanding of limits associated with the interconnect architecture, salient sets of models for global signal, clock, and power-supply distribution networks are created to describe the interconnect characteristic in future generations of technology. These new interconnect models are utilized to create an integrated architecture for global interconnects in a GSoC. Moreover, an architecture for global interconnect networks utilizing both on-chip and onboard wiring networks is investigated.