Design Techniques for High Frequency PAs and VCOs.

摘要

Today's content-centric mobile world demands Gigabit-per-second (Gbps) wireless communication systems. With sub-10GHz radio frequencies cluttered with existing wireless infrastructures such as 2.4GHz and 5GHz Wi-Fi and a multitude of LTE bands in the 1-2GHz range, focus has shifted to microwaves and mm-waves. The inverse relation between frequency and wavelength (and thus antenna size) differentiates mm-wave solutions in terms of size. For example, a 16-element antenna array only takes about 1.5cm2 at 60GHz. The pitfall, however, is the degraded active device performance at these high frequencies. Innovations at circuit-level and architecture-level are thus necessary. The dominant non-idealities that limit the performance of such radios in CMOS are the phase noise of the voltage controlled oscillator (VCO), the maximum output power of power amplifier (PA) limited by device breakdown voltage, and the non-linear behavior of the PA. Circuit and architecture level innovations presented in this research improve state-of-the-art performance in those areas.;To address the phase noise limitation, a mm-wave VCO architecture with low phase noise and large tuning range is presented. MM-wave systems rely on large channel bandwidths (e.g. 1.7GHz per channel, 7GHz total) to achieve high data rates. Channel selection using varactors and/or switched-capacitors suffers from poor phase noise performance due to the low quality factor of those elements at mm-waves. In the proposed architecture, the required frequency tuning range is divided amongst four narrow-band clusters of VCOs. Each cluster of VCOs can achieve lower phase noise due to the reduced frequency tuning range requirement. Phase noise of each cluster is further improved by using multiple cores of VCOs connected in parallel with differential transmission lines. The VCO achieves a phase noise of -101.8 dBc/Hz at 1 MHz offset with an FOM of -182dB/Hz and over 12.6% frequency tuning range (50.7 GHz to 57.5 GHz).;Another focus of this research is to improve the power amplifier (PA) performance (output power, linearity, and efficiency). Innovations in power combining techniques enable us to achieve the highest reported saturated power level of 22.6dBm in CMOS at 60GHz. Stacking transistors as a second remedy to improve the output power of the PA is considered and trade-offs in gain, reliability, and output power are treated analytically and an optimal stacking strategy for mm-wave PAs is presented. A simulation-based comparison shows the superiority of the proposed optimal stacking approach compared with the conventional stacking approach for a 60GHz SiGe PA.;A wideband self-contained PA linearization technique is presented to address mm-wave PA linearity challenges. The proposed Adaptive Gain and Phase Adjustment (AGPA) linearization technique compensates for both AM-AM and AM-PM distortion of the PA for large channel bandwidths of hundreds of megahertz at mm-waves. The gain and phase linearization loop consists of an envelope detector, an Analog Mapping Core (AMC), and a variable RC feedback network. The detection and adjustment loop has a low group delay and thus enables one of the largest linearization bandwidths published. AGPA improves the OP1dB of a stacked mm-wave PA by 2.8dB (from 9.5dBm to 12.3dBm) and reduces the IM3 products by 3dB at 8dBm output power with a tone spacing of 200MHz. Power Added Efficiency (PAE) at OP1dB is improved from 6.5% to 10.5% by enabling AGPA at 57GHz.