Test plan generation technique for complex integrated circuits.

摘要

Test strategy planning is an advanced technique to reduce the overall cost of integrated circuit (IC) devices in manufacturing test. Since test cost usually takes up a relatively high percentage of the total costs as the complexity of IC devices increases, many test methods must be taken into account to test an IC device cheaply and accurately. In the case of a device with high production volume, cost effectiveness at each manufacturing stage is a very important factor that cannot be ignored. A well organized and sophisticated decision process for selecting designs and test methods is necessary for device designers and managers to reduce the total cost. A test plan generation technique should be taken into account to help designers and managers predict the cost of a certain test plan early in the design stage. The ultimate goal for this work is to make a comparison for each test strategy that leads to a decision process on how to make and test complex IC devices economically.; An economics model for the entire process of chip manufacturing is proposed to analyze the financial costs of a product as early as possible in the design stage and taking into account the manufacturing process. The economics model makes it possible for device designers and managers to quantify the economic parameters and manufacturing values and then estimate the financial impact on the overall cost and the potential profit. The economic analysis is carried out to help make appropriate strategies at the right time for design and test.; This dissertation focuses on test strategy planning for complex integrated circuits. As circuit complexity and production volume are increased, test cost becomes a major factor in determining the total manufacturing cost. Also, design for testability (DFT) has become an essential technique in design because the short test time and high fault coverage are directly related to design technique. Hence, the decision of which DFT test method to apply is difficult to make at the beginning of IC development.; In this work, generating a new test plan technique for complex integrated circuits has been proposed using the economics model. Users can anticipate the effect on both overall cost and partial cost related with test cost parameters from each stage of design, development and manufacture. The cost-optimized test strategies for the complex chip can be determined at each manufacturing step with this technique.