Complex number arithmetic plays an important role in various signal processing tasks, such as correlations, convolutions, and digital filtering. There is a need in such applications to exploit parallelism in implementing sequences of arithmetic expressions, as well as to reduce the bandwidth of the data path. Reconfigurable architectures are emerging as a viable technology for mapping numeric-intensive computations onto hardware. In order to provide efficient implementations that can accommodate changes with a minimal amount of redesign, the methodology for deriving algorithms and corresponding implementations must be flexible toward change.; In this dissertation, we present an efficient representation which treats the real and imaginary components as a unified number. We propose algorithms for various complex number on-line floating-point arithmetic operations. The algorithms are translated into actual implementations mapped onto reconfigurable hardware. The implementations are applied toward computing the complex singular value decomposition of a matrix, with a significant reduction in cost compared to networks of real number on-line and parallel arithmetic approaches.
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