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All computations are created equal, but some are more equal than others: Novel designs and uses of communication in auxiliary processing systems.

机译:创建的所有计算都是相同的,但有些计算却比其他计算更平等:新颖的设计和辅助处理系统中通信的使用。

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摘要

As clock speeds and transistor densities continue to increase, cheap, fast, parallel single-chip systems are being introduced in the commodity market. Placing high-performance, homogeneous parallel processing power on-chip has the economic advantage of designing a single component and replicating it several times on the chip, saving design and verification time. There is the potential, however, for heterogeneous designs as well. Computation is not always the bottleneck for performance—memory bandwidth and latency are. Adding computation power on-chip does helps little relieve memory pressure. In addition, parallelization of existing programs is not trivial. To increase single-thread performance in commodity systems, high-performance parallelism must be achievable by the average programmer.; In this thesis, I examine three heterogeneous “auxiliary” processor systems. All three systems have the same goal—parallelize a computation to better utilize the available resources—but the routes taken are very different. The first, Active Pages, places processing in memory to allow computations to take advantage of high on-chip bandwidth and low latencies. This is designed for a sophisticated programmer to get the most out of a new architecture. The second, a software security system, leverages a very small amount of chip space to dramatically increase the performance of dynamic pointer checking. This parallelism is provided entirely by the system, and is transparent to the programmer, making a major high-overhead debugging task more efficient. Finally, I present IOP (Instruction-level Object Parallelism), a system that provides an instruction-level interface to exploit object-level parallelism. This leverages the practices already used in object-oriented programming to expose parallelism with the low overhead communication and synchronization in modern processors, providing semi-transparent, high-performance parallelization.; In all three systems, communication mechanisms are compared based on hardware costs, performance, and programmability. Because the target is commodity desktop systems, existing communication mechanisms will be used as often as possible.
机译:随着时钟速度和晶体管密度的不断提高,廉价,快速,并行的单芯片系统已被引入商品市场。在芯片上放置高性能,均质的并行处理能力具有设计单个组件并将其复制到芯片上多次的经济优势,从而节省了设计和验证时间。但是,异构设计也有潜力。计算并不总是性能的瓶颈,内存带宽和延迟是瓶颈。在芯片上增加计算能力确实没有什么帮助减轻内存压力。此外,现有程序的并行化并非易事。为了提高商品系统中的单线程性能,普通程序员必须能够实现高性能的并行性。在本文中,我研究了三种异构的“辅助”处理器系统。这三个系统都具有相同的目标-使计算并行化以更好地利用可用资源-但采用的路线却大不相同。第一个是活动页面,将处理放在内存中,以允许计算利用高片上带宽和低延迟。这是为熟练的程序员设计的,以充分利用新架构。第二个是软件安全系统,它利用非常少的芯片空间来显着提高动态指针检查的性能。这种并行性完全由系统提供,并且对程序员透明,从而使主要的高开销调试任务更加高效。最后,我介绍IOP(指令级对象并行性),这是一个提供指令级接口以利用对象级并行性的系统。这利用了面向对象编程中已经使用的实践,以现代处理器中的低开销通信和同步来揭示并行性,从而提供了半透明,高性能的并行化。在所有三个系统中,将根据硬件成本,性能和可编程性来比较通信机制。因为目标是商品桌面系统,所以将尽可能多地使用现有的通信机制。

著录项

  • 作者

    Keen, Diana Marie.;

  • 作者单位

    University of California, Davis.;

  • 授予单位 University of California, Davis.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2002
  • 页码 123 p.
  • 总页数 123
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

  • 入库时间 2022-08-17 11:46:13

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