A continuous-time sigma-delta A-D converter in an indium phosphide-based HBT technology.

摘要

A 2nd order continuous-time Σ − Δ modulator, clocked at 8 GHz, is demonstrated. A static frequency divider, operating to a maximum clock frequency of 87 GHz, is also demonstrated. These designs are motivated by the explosive growth in the fiber-optic and telecommunication market.; The first part of the thesis focuses on the development of InP-based Double Heterojunction Bipolar Transistors (DHBTs) in a substrate-transfer process as well as in a narrow-mesa process. The design of a Static Frequency Divider in the narrow-mesa process is also discussed. The main results of this part of the thesis are: (i) a device with 165 GHz f _τ, 300 GHz f_max and 9 V BV _CEO in a substrate-transfer process, (ii) a device with 200 GHz f_τ, 205 GHz f_max and 6 V BV_CEO in a narrow-mesa process, and (iii) a static frequency divider with a maximum clock frequency of 87 GHz.; The focus shifts in the second part of the thesis to the design of a 2nd order continuous-time Σ − Δ modulator in the narrow-mesa process. The problem of metastability and excess loop delay is considered. Solutions to these problems, based on theoretical analysis, are proposed and their efficacy is studied using full-loop MATLAB and SPICE simulations. Finally, the measurement techniques and the results are discussed. The measured SNR, and effective bits of resolution, at 250 Msps sample-rate are 48 dB and 7.7 bits, respectively. A peak intermodulation-suppression of >80 dBc is observed.