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Emulating an output queued packet switch with systems containing input and output queueing.

机译:用包含输入和输出排队的系统模拟输出排队的分组交换机。

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Modern Data Communication networks require packet switches capable of providing quality of service (QoS) guarantees to arriving packets. Economic realities argue for scalable packet switch architectures with practical manufacturing costs. The designer of a packet switch must therefore choose an architecture meeting specific cost and performance goals. To this end it is necessary to understand the performance capabilities of different architectures and to compare their complexity for critical components such as memory and scheduling.; Packet switch architectures containing input and output queueing are considered practical for their low speed memory requirements. This thesis evaluates the performance limits of two types of combined input/output-queued (CIOQ) switches: those containing crossbar switch fabrics and those containing a limited memory switch fabric. In particular, we are interested in necessary and sufficient conditions that enable these architectures to satisfy two important performance goals: that is, to achieve 100% throughput (full utilization of the output lines) and to exactly emulate the “ideal” output-queued (OQ) switch architecture.; We attain our results by developing new performance evaluation methods and by presenting new scheduling algorithms for both types of CIOQ switches. We present a new network structure, termed the Constrained Clos network, that is functionally equivalent to a crossbar-based CIOQ packet switch. Using insights gained from the Constrained Clos network, we establish necessary and sufficient conditions for an N × N crossbar CIOQ switch, operated by specific scheduling algorithms, to achieve both 100% throughput and to emulate an OQ switch. Moreover, we establish that a 2 × 2 crossbar CIOQ switch requires less speedup for both 100% throughput and for OQ switch emulation. Additionally, we develop new distributed scheduling algorithms that allow a limited memory CIOQ switch to exactly emulate an OQ switch. We then compare the complexity of the OQ switch, the crossbar-based CIOQ switch and the limited memory CIOQ switch when these systems perform equivalently. The limited memory CIOQ switch architecture is argued to be the most practical given current technology.
机译:现代数据通信网络需要能够为到达的数据包提供服务质量(QoS)保证的数据包交换机。经济现实要求具有实际制造成本的可扩展的分组交换机体系结构。因此,分组交换机的设计者必须选择一种满足特定成本和性能目标的体系结构。为此,有必要了解不同体系结构的性能,并比较它们对于诸如内存和调度之类的关键组件的复杂性。包含输入和输出排队的分组交换架构因其低速存储需求而被认为是实用的。本文评估了两种类型的组合输入/输出排队(CIOQ)开关的性能极限:包含交叉开关结构的开关和包含有限内存开关结构的开关。尤其是,我们对使这些架构满足两个重要性能目标的必要和充分条件感兴趣:即实现100%的吞吐量(输出线的充分利用)并精确地模拟“理想”的输出队列( OQ)交换机体系结构。我们通过开发新的性能评估方法并针对这两种类型的CIOQ交换机提出新的调度算法来获得结果。我们提出了一种新的网络结构,称为约束Clos网络,该结构在功能上等同于基于交叉开关的CIOQ数据包交换机。利用从约束Clos网络中获得的见解,我们为 N × N 交叉CIOQ开关建立了充要条件,并通过特定的调度算法进行操作,以实现100%的吞吐量并模拟一个OQ开关。此外,我们建立了一个2×2交叉开关CIOQ交换机,对于100%的吞吐量和OQ交换机仿真,都要求较少的加速。此外,我们开发了新的分布式调度算法,该算法允许有限内存的CIOQ交换机精确模拟OQ交换机。然后,当这些系统性能相同时,我们将比较OQ开关,基于交叉开关的CIOQ开关和有限内存CIOQ开关的复杂性。有限内存的CIOQ开关架构被认为是当前技术中最实用的。

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