High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen, Bit Error Rate (BER) performance is of paramount importance in any communication interface. The bit errors in HSSIs are in large part due to jitter. This thesis investigates the topic of accelerating the jitter and BER testing and characterization [1].;The thesis also presents an external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay lines. The scheme can be applied to test HSSIs with data rate up to 12.5 Gbps. It is also suitable for multi-lane HSSI testing with a lower cost than pure ATE solutions. By using high-speed relays, we combine the proposed ATE based approaches and the loopback approach along with an FPGA-based BER tester to provide a more versatile scheme for HSSI post-silicon validation, testing and debugging [5]. In addition, we further explore the unparallel advantages of our digital Gaussian noise generator in low BER evaluation [6].;The thesis first proposes a new algorithm, suitable for extrapolating the receiver jitter tolerance performance from higher BER regions down to the 10-12 level or lower [2]. This algorithm enables us to perform the jitter tolerance characterization and production test more than 1000 times faster [3]. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms [4] while the test usually takes seconds. All the receiver and transmitter testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with speed up to 6 Gigabits per second (Gbps).
展开▼
