Transient Performance Improvement Circuit (TPIC)s for DC-DC converter applications.

摘要

Gordon Moore famously predicted the exponential increase in transistor integration and computing power that has been witnessed in recent decades [1]. In the near future, it is expected that more than one billion transistors will be integrated per chip, and advanced microprocessors will require clock speeds in excess of several GHz. The increasing number of transistors and high clock speeds will necessitate the consumption of more power. By 2014, it is expected that the maximum power consumption of the microprocessor will reach approximately 150W, and the maximum load current will be around 150A. Today's trend in power and thermal management is to reduce supply voltage as low as possible to reduce delivered power. It is anticipated that the Intel cores will operate on 0.8V of supply voltage by 2014 [2].;A significant challenge in Voltage Regulator Module (VRM) development for next generation microprocessors is to regulate the supply voltage within a certain tolerance band during high slew rate load transitions, since the required supply voltage tolerance band will be much narrower than the current requirement. If VR output impedance is maintained at a constant value from DC to high frequency, large output voltage spikes can be avoided during load cur- rent transients. Based on this, the Adaptive Voltage Position (AVP) concept was developed to achieve constant VR output impedance to improve transient response performance [3]. However, the VR output impedance can not be made constant over the entire frequency range with AVP design, because the AVP design makes the VR output impedance constant only at low frequencies. To make the output impedance constant at high frequencies, many bulk capacitors and ceramic capacitors are required.;The tight supply voltage tolerance for the next generation of microprocessors during high slew rate load transitions requires fast transient response power supplies. A VRM can not follow the high slew rate load current transients, because of the slow inductor current slew rate which is determined by the input voltage, output voltage, and the inductance. The remaining inductor current in the power delivery path will charge the output capacitors and develop a voltage across the ESR. As a result, large output voltage spikes occur during load current transients. Due to their limited control bandwidth, traditional VRs can not sufficiently respond rapidly to certain load transients. As a result, a large output voltage spike can occur during load transients, hence requiring a large amount of bulk capacitance to decouple the VR from the load [2]. If the remaining inductor current is removed from the power stage or the inductor current slew rate is changed, the output voltage spikes can be clamped, allowing the output capacitance to be reduced.;A new design methodology for a Transient Performance Improvement Circuit(TPIC) based on controlling the output impedance of a regulator is presented. The TPIC works in parallel with a voltage regulator (VR)'s ceramic capacitors to achieve faster voltage regulation without the need for a large bulk capacitance, and can serve as a replacement for bulk capacitors. The specific function of the TPIC is to mimic the behavior of the bulk capacitance in a traditional VRM by sinking and sourcing large currents during transients, allowing the VR to respond quickly to current transients without the need for a large bulk capacitance. This will allow fast transient response without the need for a large bulk capacitor. The main challenge in applying the TPIC is creating a design which will not interfere with VR operation.;A TPIC for a 4 Switch Buck-Boost (4SBB) converter is presented which functions by con- trolling the inductor current slew rate during load current transients. By increasing the inductor current slew rate, the remaining inductor current can be removed from the 4SBB power delivery path and the output voltage spike can be clamped. A second TPIC is presented which is designed to improve the performance of an LDO regulator during output current transients.;A TPIC for a LDO regulator is proposed to reduce the over voltage spike settling time. During a load current step down transient, the only current discharging path is a light load current. However, it takes a long time to discharge the current charged in the output capacitors with the light load current. The proposed TPIC will make an additional current discharging path to reduce the long settling time. By reducing the settling time, the load current transient frequency of the LDO regulator can be increased.;A Ripple Cancellation Circuit (RCC) is proposed to reduce the output voltage ripple. The RCC has a very similar concept with the TPIC which is sinking or injecting additional current to the power stage to compensate the inductor ripple current.;The proposed TPICs and RCC have been implemented with a 0.6m CMOS process. A single-phase VR, a 4SBB converter, and a LDO regulator have been utilized with the proposed TPIC to evaluate its performance. The theoretical analysis will be confirmed by Cadence simulation results and experimental results.