Silicon-on-silicon system packaging.

摘要

A novel process for homogeneous integration of commercially available off-the-shelf integrated circuits on a silicon (Si) substrate, utilizing wafer bonding, has been developed. The integration of discrete ICs with different functionality on a silicon substrate is inherently more reliable than traditional packaging because it eliminates wires bonds and discrete packages; allowing for higher density interconnections. This integration assembly also reduces the thermal mismatch between the package components and the associated reliability problems.; The process begins with the formation of cavities into a Si substrate to house the Si devices. A Si wafer is patterned, completely etched through and bonded to a Si handle wafer at 1100°C. During this step, a covalent bond is formed at the interface of the two wafers while the sidewalls of the cavities are covered with about a micron of thermal oxide to ensure the electrical isolation of the Si chips from the housing wafer. Afterwards, the devices are bonded via low temperature wafer bonding into the resulted cavities of the housing wafer. After bonding, the trenches formed between the inserted chips and the surrounding silicon body are filled and the module surface is planarized to insure reliable chip-to-chip interconnection. Aluminum is then sputtered and patterned by wet etching to define the metal lines connecting the integrated circuits. Multiple interconnect layers can be implemented by repeating the last two processing steps.; The structural and thermal performance of the silicon-on-silicon multichip module was investigated using the finite element analysis package ANSYS. Thermomechanical analysis has been performed on the structure to evaluate its behavior under typical operating conditions as well as to determine the key geometrical parameters that influence the package reliability. Thermal simulations have been performed to ascertain the most suitable cooling solution for the module.; The resulting structure exhibits excellent isolation and a high interconnect density of the integrated Si components. The bond between the devices and the substrate of the module was found to be very reliable, no bond ever failing during processing or testing. Line continuity tests on interconnect between adjacent chips has been proven with a minimum line width of 15 microns.