Incremental diagnosis in digital VLSI circuits.

摘要

Today's complex VLSI design and manufacturing environment demands an efficient and scalable approach to fault and design error diagnosis. This thesis proposes an incremental methodology for multiple fault/error diagnosis. This simulation-based approach is simple to implement, scalable in resolution and efficient in performance. A general incremental algorithm is devised along with theorems and heuristics that prune the diagnosis space. Three fault diagnosis and one design error diagnosis algorithms are developed using the general algorithm as a template. Fault models are used to diagnose stuck-at and transition faults, and to rectify design errors. For open-interconnect fault, a model-free algorithm is developed to capture possibly faulty paths, along with a novel heuristic to prune the search space.; Experiments conducted on ISCAS'85 and ISCAS'89 benchmark circuits confirm the efficiency of the proposed incremental approach. The diagnostic resolution is also shown to scale well with increasing number of faults/errors.