Video-rate stereo vision on reconfigurable hardware.

摘要

This thesis describes the implementation of a stereo depth measurement algorithm in hardware on Field-Programmable Gate Arrays (FPGAs). This system generates 8-bit, sub-pixel disparities on 256 by 360 pixel images at video rate (30 frames/sec). The algorithm implemented is a multi-resolution, multi-orientation phase-based technique called Local Weighted Phase-Correlation. Hardware implementation speeds up the performance approximately 60 to 900 times that of the same algorithm running in software. In this thesis, we describe the programmable hardware platform, the base stereo vision algorithm and the design of the hardware. We include various trade-offs required to make the hardware small enough to fit on our system and fast enough to work at video rate. We show the depth map results from the functioning hardware. Although this research is specifically focused on phase-based stereo vision FPGA realizations, most of the design issues are common to other DSP and Vision applications.