Memory hierarchy management through off-line computational learning.

摘要

The memory hierarchy was introduced to help bridge the performance gap between processors and their inexpensive memories. The problem worsens as processor speeds are increasing at a faster rate than memory speeds, and as memory designs are unable to keep up with the growing demands of increasingly irregular applications.; Data Prefetching is an important technique for addressing this growing problem, and is the focus of this dissertation. Specifically, a novel hardware-assisted data prefetching mechanism that is driven by off-line or compile-time computational learning is presented. Representations of the prediction patterns that proposed techniques “learn” are stochastic, and range from simple predictors to sophisticated Hidden Markov Models. In addition, a software-based adaptation of this technique is also presented which is coupled with lightweight architectural extensions ubiquitous to generic EPIC processors thus eliminating the need for additional hardware support. Overall, we were able to improve performances of conventional as well as irregular workloads from 11% to 23% on the average.