Low power and high performance circuit design for process scalability.

摘要

The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative developments in low power design recently.; In this thesis, we discuss major sources of power dissipation in VLSI systems, and present new low power design techniques on the technology and circuit level. We present a low power 1.85GHz 32-bit CLA adder using Dual Path All-N-Logic; We introduces leakage-proof domino circuit design for deep sub-100nm technologies, which can suppress both subthreshold leakage and gate leakage in standby mode; We describe a four-phase keeper design for high fan-in dynamic gates. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay; We present a new domino failure mechanism in deep sub-100nm technologies and its solution; We propose a new Clock Delayed N-P Dynamic Logic, and apply it to a 32-bit carry lookahead adder with an improved sparse tree structure; We introduce a current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip Communications. The current mode scheme is faster and consumes less power by reducing the voltage swing on the transmission line between two chips.